1. Field of the Invention
The present invention relates to the technical field of embedded memory and, more particularly, to an SRAM compatible embedded DRAM system with hidden refresh and dual port capabilities.
2. Description of Related Art
For a system on chip (SoC) application, it requires integration of multiple functional blocks into a single IC. A commonly used functional block typically includes a processor, a controller, a memory block and various functional logic blocks, which are all incorporated into one chip. The memory block can include an SRAM, a non-volatile memory and/or a register based memory (RBM). Typically, the RBM is used in a situation requiring small unit of high speed storage, such as a register file and/or a small-sized table used by one or more functional logic blocks in the SoC.
Generally, a SoC requires larger volatile or non-volatile memory blocks. However, for a cost consideration, a designer reduces the allocated areas for the memory blocks as small as possible. If a memory block is a refreshed volatile memory, the memory block is typically implemented with a 6-T SRAM cell.
For saving the cost, a method uses multiple dynamic random access memory (DRAM) cells and a static random access memory (SRAM) interface to form a 1T SRAM system. Such a method requires an automatic refresh mechanism to automatically refresh the DRAM cells in the 1T SRAM system to thereby avoid the lost data.
The 1T SRAM system, which is a single port memory system, is used in U.S. Pat. No. 6,075,740 granted to Leung for a “Method and apparatus for increasing the time available for refresh for 1-t SRAM compatible devices” to thereby save the cost, but it can easily cause an access bottleneck.
The access bottleneck is caused when many master devices in the SoC access an embedded memory. Accordingly, as shown in FIG. 1, US Patent Application Publication No. 2008/0005492 published Jan. 3, 2008, entitled “Dual-port SRAM memory using single-port memory cell” adds an arbiter 505, a multiplexer 502, a refresh controller 530 and interface circuits 510, 520 to allow the single-port memory array 501 to act as a dual-port SRAM memory.
Namely, in US 2008/0005492, the dual-port SRAM memory is implemented using the single-port memory array 501. However, with increasing the access clock on the SoC, such a memory system presents an access bottleneck in the SoC, so that the SoC clock cannot be effectively increased.
Therefore, it is desirable to provide an improved system to mitigate and/or obviate the aforementioned problems.